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1 opa686 international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson blvd., tucson, az 85706 ? tel: (520) 746-1111 ? twx: 910-952-1111 internet: http://www.burr-brown.com/ ? faxline: (800) 548-6133 (us/canada only) ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? immediate product info: (800) 548-6132 opa686 wideband, low noise, voltage feedback operational amplifier applications l high dynamic range adc preamp l low noise, wideband, transimpedance amplifier l wideband, high gain amplifier l low noise differential receiver l vdsl line receiver l ultrasound channel amplifier l improved replacement for the clc425 features l high bandwidth: 250mhz (g = +10) l low input voltage noise: 1.3nv/ ? hz l very low distortion: C90dbc (5mhz) l high slew rate: 600v/ m s l high dc accuracy l low supply current: 12ma l high gain bandwidth product: 1600mhz l stable for gains 3 7 description the opa686 combines very high gain bandwidth and large signal performance with very low input voltage noise while dissipating a low 12ma supply current. the classical differen- tial input stage, along with two stages of forward gain and a high power output stage, combine to make the opa686 an exceptionally low distortion amplifier with excellent dc accu- racy and output drive. the voltage feedback architecture allows all standard op amp applications to be implemented with very high performance. the combination of low input voltage and current noise, along with a 1.6ghz gain bandwidth product, make the opa686 an ideal amplifier for wideband transimpedance stages. as a volt- age gain stage, the opa686 is optimized for a flat response at a gain of +10 and is guaranteed stable down to a noise gain of +7. high gain, 20mhz transimpedance amplifier tm a new external compensation technique can be used to give a very flat frequency response below the minimum stable gain for the opa686, further improving its already exceptional distortion performance. using this compensation makes the opa686 one of the premier 12- to 14-bit analog-to-digital converter input drivers. the supply current for the opa686 is precisely trimmed to 12.4ma at +25 c. this, along with carefully defined supply current tempcos in the input and output stages, combine to provide exceptional performance over the full specified temperature range. opa686 opa686 ? 1997 burr-brown corporation pds-1370d printed in u.s.a. may, 2000 opa686 +5v ?v v o 50k w 0.1 f 100pf 50k w 0.2pf 10pf photodiode i s ? b supply decoupling not shown. l 100 95 90 85 80 75 70 65 60 frequency (mhz) 0.1 1 10 100 20?og (z t ) 5db/div 20log (50k w ) = 94db w opa686 related products input noise gain bandwidth singles duals voltage (nv/ ? hz) product (mhz) OPA643 2.3 800 opa2686 1.3 1600 opa687 0.95 3600 for most current data sheet and other product information, visit www.burr-brown.com sbos063
2 opa686 opa686u, n typ guaranteed 0 c to C40 c to min/ test parameter conditions +25 c +25 c (2) 70 c (3) +85 c (3) units max level (1) specifications: v s = 5v r f = 453 w , r l = 100 w, and g =+10, unless otherwise noted. figure 1 for ac performance. ac performance (figure 1) closed-loop bandwidth g = +7, r g = 50 w , v o = 200mvp-p 425 mhz typ c g = +10, r g = 50 w , v o = 200mvp-p 250 200 170 140 mhz min b g = +20, r g = 50 w , v o = 200mvp-p 100 80 65 55 mhz min b gain bandwidth product g 3 +40 1600 1250 1100 1000 mhz min b bandwidth for 0.1db gain flatness g = +10, r l = 100 w , v o = 200mvp-p 40 35 30 25 mhz min b peaking at a gain of +7 2 db typ c harmonic distortion g = +10, f = 5mhz, v o = 2vp-p 2nd harmonic r l = 100 w C72 C67 C65 C60 dbc max b r l = 500 w C90 C85 C80 C75 dbc max b 3rd harmonic r l = 100 w C95 C90 C85 C80 dbc max b r l = 500 w C110 C105 C100 C95 dbc max b two-tone, 3rd-order intercept g = +10, f = 10mhz 43 40 39 37 dbm min b input voltage noise f > 1mhz 1.3 1.5 1.6 1.7 nv/ ? hz max b input current noise f > 1mhz 1.8 2.3 2.4 2.5 pa/ ? hz max b rise/fall time 0.2v step 1.4 1.75 2 2.5 ns max b slew rate 2v step 600 500 400 310 v/ m s min b settling time to 0.01% 2v step 18 ns typ c 0.1% 2v step 16 14 21 25 ns max b 1% 2v step 11 12 14 18 ns max b differential gain g = +10, ntsc, r l = 150 w 0.02 % typ c differential phase g = +10, ntsc, r l = 150 w 0.02 deg typ c dc performance (4) open-loop voltage gain (a ol )v o = 0v 80 75 70 70 db min a input offset voltage v cm = 0v 0.35 1.0 1.2 1.5 mv max a average offset voltage drift v cm = 0v 5 10 m v/ c max b input bias current v cm = 0v C10 C17 C18 C20 m a max a input bias current drift v cm = 0v 50 100 na/ c max b input offset current v cm = 0v 0.5 1.0 1.5 1.8 m a max a input offset current drift v cm = 0v 5 10 na/ c max b input common-mode input range (cmir) (5) 3.2 3.0 2.9 2.8 v min a common-mode rejection (cmr) v cm = 1v, input referred 100 90 85 75 db min a input impedance differential-mode v cm = 0v 6 || 2 k w || pf typ c common-mode v cm = 0v 2.9 || 1 m w || pf typ c output output voltage swing 3 400 w load 3.5 3.2 3.1 3.0 v min a 100 w load 3.3 3.0 2.8 2.8 v min a current output, sourcing v o = 0v 80 60 55 50 ma min a current output, sinking v o = 0v C80 C60 C55 C40 ma min a closed-loop output impedance g = +10, f = 100khz 0.008 w typ c power supply specified operating voltage 5 v typ c maximum operating voltage 6 6 6 v max a max quiescent current v s = 5v 12.4 12.9 13 13.9 ma max a min quiescent current v s = 5v 12.4 11.9 11.9 11 ma min a power supply rejection ratio +psrr, Cpsrr |v s | = 4.5 to 5.5, input referred 78 70 70 65 db min a thermal characteristics specified operating range: u, n package C40 to +85 c typ c thermal resistance, q ja junction-to-ambient u 8-pin, so-8 125 c/w typ c n 5-pin, sot23 150 c/w typ c notes: (1) test levels: (a) 100% tested at 25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information. (2) junction temperature = ambient for 25 c guaranteed specifications. (3) junction temperature = ambient at low temperature limit: junction temperature = ambient +23 c at high temperature limit for over temperature guaranteed specifications. (4) current is considered positive out-of-node. v cm is the input common-mode voltage. (5) tested < 3db below minimum specified cmr at cmir limits.
3 opa686 the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. pin configurations 1 2 3 4 8 7 6 5 nc inverting input non-inverting input ? s dnc +v s output nc dnc: do not connect nc: no connection 1 2 3 5 4 output ? s non-inverting input +v s inverting input 1 2 3 5 4 pin orientation/package marking a86 top view sot23-5 top view so-8 package drawing temperature package ordering transport product package number (1) range marking number (2) media opa686u so-8 surface mount 182 C40 c to +85 c opa686u opa686u rails " """" opa686u/2k5 tape and reel opa686n 5-lead sot23-5 331 C40 c to +85 c a86 opa686n/250 tape and reel " " " " opa686n/3k tape and reel notes: (1) for detailed drawing and dimension table, please see end of data sheet, or appendix c of burr-brown ic data book. (2 ) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2k5 indicates 2500 devices per reel). ordering 2500 pieces of opa686u/2k5 will get a single 2500-piece tape and reel. for detailed tape and reel mechanical information, refer to appendix b of burr-brown ic data book. package/ordering information absolute maximum ratings power supply ............................................................................... 6.5v dc internal power dissipation ...................................... see thermal analysis differential input voltage .................................................................. 1.2v input voltage range ............................................................................ v s storage temperature range: u, n ................................ C40 c to +125 c lead temperature (soldering, 10s) .............................................. +300 c junction temperature (t j ) ........................................................... +175 c electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
4 opa686 typical performance curves: v s = 5v at t a = +25 c, g = +10, r f = 453 w , and r l = 100 w , unless otherwise noted. 6 3 0 ? ? ? ?2 ?5 ?8 ?1 ?4 non-inverting small-signal frequency response frequency (mhz) normalized gain (3db/div) 0.5 10 100 500 g = +50 see figure 1 r g = 50 w v o = 0.2vp-p g = +20 g = +7 g = +10 26 23 20 17 14 11 8 5 2 ? ? non-inverting large-signal frequency response frequency (mhz) gain (3db/div) 0.5 10 100 500 r g = 50 w g = +10v/v v o = 0.2vp-p v o = 1vp-p v o = 2vp-p v o = 5vp-p see figure 1 30 29 26 23 20 17 14 11 8 5 2 inverting large-signal frequency response frequency (mhz) gain (3db/div) 0.1 10 100 500 r g = r s = 50 w g = ?0v/v v o = 0.2vp-p v o = 1vp-p v o = 2vp-p v o = 5vp-p see figure 2 100 0 ?00 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 non-inverting pulse response time (5ns/div) output voltage (100mv/div) output voltage (500mv/div) g = +10v/v large signal ?v small signal ?00mv right scale left scale see figure 1 100 0 ?00 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 inverting pulse response time (5ns/div) output voltage (100mv/div) output voltage (500mv/div) g = ?0v/v large signal ?v small signal ?00mv right scale left scale see figure 2 6 3 0 ? ? ? ?2 ?5 ?8 ?1 ?4 inverting small-signal frequency response frequency (mhz) normalized gain (3db/div) 0.5 10 100 500 r g = r s = 50 w v o = 0.2vp-p g = ?2 g = ?0 g = ?0 see figure 2
5 opa686 typical performance curves: v s = 5v (cont) at t a = +25 c, g = +10, r g = 50 w , and r l = 100 w , unless otherwise noted. see figure 1. ?0 ?0 ?0 ?00 ?10 output voltage (vp-p) 0.1 10 1 5mhz 2nd harmonic distortion vs output voltage 2nd harmonic distortion (dbc) r l = 200 w r l = 100 w r l = 500 w ?0 ?0 ?0 ?00 ?10 output voltage (vp-p) 0.1 10 1 5mhz 3rd harmonic distortion vs output voltage 3rd harmonic distortion (dbc) r l = 200 w r l = 100 w r l = 500 w ?0 ?0 ?0 ?0 ?00 output voltage (vp-p) 0.1 10 1 10mhz 2nd harmonic distortion vs output voltage 2nd harmonic distortion (dbc) r l = 200 w r l = 100 w r l = 500 w ?0 ?0 ?0 ?0 ?00 output voltage (vp-p) 0.1 10 1 10mhz 3rd harmonic distortion vs output voltage 3rd harmonic distortion (dbc) r l = 200 w r l = 500 w r l = 500 w ?0 ?0 ?0 ?0 ?0 output voltage (vp-p) 0.1 10 1 20mhz 2nd harmonic distortion vs output voltage 2nd harmonic distortion (dbc) r l = 200 w r l = 100 w r l = 500 w ?0 ?0 ?0 ?0 ?0 20mhz 3rd harmonic distortion vs output voltage output voltage (vp-p) 0.1 1 10 3rd harmonic distortion (dbc) r l = 100 w r l = 200 w r l = 500 w
6 opa686 typical performance curves: v s = 5v at t a = +25 c, g = +10, r f = 453 w , and r l = 100 w , unless otherwise noted. see figure 1. 60 50 40 30 20 10 0 r s vs capacitive load capacitive load (pf) 1 10 100 r s ( w ) 50 45 40 35 30 25 20 15 0 two-tone, 3rd-0rder intermodulation intercept vs frequency frequency (mhz) 0 5 10 15 20 25 30 35 40 45 50 intercept (dbm) opa686 p i p o 50 w 50 w 50 w 453 w 50 w ?0 ?0 ?0 ?0 ?0 2nd harmonic distortion vs frequency frequency (mhz) 11020 2nd harmonic distortion (dbc) g = +50 v o = 2vp-p r l = 100 w g = +10 g = +20 ?0 ?0 ?0 ?0 ?0 3rd harmonic distortion vs frequency frequency (mhz) 11020 3rd harmonic distortion (dbc) g = +10 v o = 2vp-p r l = 100 w g = +50 g = +20 10 1 input voltage and current noise density frequency (hz) 100 10m 1k 10k 100k 1m current noise (pa/ ? hz) voltage noise (nv/ ? hz) 1.8pa/ ? hz 1.3nv/ ? hz current noise voltage noise 22 21 20 19 18 17 16 15 14 13 12 frequency (mhz) frequency response vs capacitive load 1 100 10 500 gain to capacitive load (1db/div) c l = 10pf c l = 50pf c l = 20pf c l = 100pf opa686 r s v in v o c l 1k w 453 w 50 w 1k w is optional
7 opa686 typical performance curves: v s = 5v (cont) at t a = +25 c, g = +10, r f = 453 w , and r l = 100 w , unless otherwise noted. see figure 1. 14 12 10 8 6 4 2 0 140 120 100 80 60 40 20 0 power supply and output current vs temperature temperature ( c) ?0 ?5 0 25 50 75 100 125 power supply current (ma) output current (ma) power supply current output current sourcing output current sinking 1.3 1.1 0.9 0.7 0.5 0.3 0.1 ?.1 13 11 9 7 5 3 1 ? input dc errors vs temperature temperature ( c) ?0 ?5 0 25 50 75 100 125 v os (mv) input bias and input offset current ( a) input bias current offset voltage input offset current 90 80 70 60 50 40 30 20 10 0 0 ?0 ?0 ?0 ?20 ?50 ?80 ?10 ?40 ?70 open-loop gain and phase frequency (hz) 100 10m 100m 1g 1k 10k 100k 1m open-loop gain (10db/div) open-loop phase (30?div) | a ol | e a ol 10 1.0 0.1 0.01 0.001 closed-loop output impedance frequency (hz) 10m 100m 10k 100k 1m output impedance ( w ) opa686 450 w 50 w 50 w z o 10 7 10 6 10 5 10 4 10 3 differential and common-mode input impedance frequency (hz) 100 10m 10m 1k 10k 100k 1m input impedance ( w ) common-mode differential 110 100 90 80 70 60 50 40 30 20 10 cmrr and psrr frequency (hz) 100 10m 100m 1k 10k 100k 1m power supply rejection ratio (db) cmrr +psrr ?srr
8 opa686 applications information wideband, non-inverting operation the opa686 provides a unique combination of features low input voltage noise along with a very low distortion output stageto give one of the highest dynamic range op amps available. its very high gain bandwidth product (gbp) can be used either to deliver high signal bandwidths at high gains, or to deliver very low distortion signals at moderate frequencies and lower gains. to achieve the full perfor- mance of the opa686, careful attention to pc board layout and component selection is required as discussed in the remaining sections of this data sheet. figure 1 shows the non-inverting gain of +10 circuit used as the basis of the electrical specifications and most of the typical performance curves. most of the curves were char- acterized using signal sources with 50 w driving impedance, and with measurement equipment presenting a 50 w load impedance. in figure 1, the 50 w shunt resistor at the v i terminal matches the source impedance of the test generator, while the 50 w series resistor at the v o terminal provides a matching resistor for the measurement equipment load. generally, data sheet voltage swing specifications are at the output pin (v o in figure 1), while output power (dbm) specifications are at the matched 50 w load. the total 100 w load at the output, combined with the 503 w total feedback network load, presents the opa686 with an effective output load of 83 w for the circuit of figure 1. voltage feedback op amps, unlike current feedback designs, can use a wide range of resistor values to set their gain. the circuit of figure 1, and the specifications at other gains, use the constraint that r g should always be set to 50 w and r f adjusted to get the desired gain. using this guideline will guarantee that the noise added at the output due to johnson noise of the resistors will not significantly increase the total noise over that due to the 1.3nv/ ? hz input voltage noise for the op amp itself. wideband, inverting gain operation operating the opa686 as an inverting amplifier has several benefits and is particularly appropriate when a matched input impedance is required. figure 2 shows the inverting gain circuit used as the basis of the inverting mode typical performance curves. figure 1. non-inverting, g = +10 specification and test circuit. figure 2. inverting, g = C20 characterization circuit. driving this circuit from a 50 w source, and constraining the gain resistor (r g ) to equal 50 w , will give both a signal bandwidth and noise advantage. r g acts as both the input termination resistor and the gain setting resistor for the circuit. although the signal gain (v o /v i ) for the circuit of figure 2 is double that for figure 1, the noise gains are in fact equal when the 50 w source resistor is included. this has the interesting effect of doubling the equivalent gbp of the amplifier. this can be seen in comparing the g = +10 and g = C20 small-signal frequency response curves. both show approximately 250mhz bandwidth, but the inverting configuration of figure 2 gives 6db higher signal gain. if the signal source is actually the low impedance output of another amplifier, r g should be increased to the minimum load resistance value allowed for that amplifier and r f should be adjusted to achieve the desired gain. for stable operation of the opa686, it is critical that this driving amplifier show a very low output impedance at frequencies beyond the expected closed-loop bandwidth for the opa686. wideband, high sensitivity, transimpedance design the high gain bandwidth product (gbp) and the low input voltage and current noise for the opa686 make it an ideal wideband transimpedance amplifier for low to moderate transimpedance gains. very high transimpedance gains (> 100k w ) will benefit from the low input noise current of a fet-input op amp such as the opa655. unity gain stability in the op amp is not required for application as a opa686 +5v ?v ? s +v s 50 w v o v i 50 w + 0.1? + 6.8? 6.8? r g 50 w r f 453 w 50 w source 50 w load 0.1? opa686 +5v ?v +v s ? s 91 w 50 w v o v i + 6.8? 0.1? + 6.8? 0.1? 0.1? r f 1k w r g 50 w 50 w source 50 w load
9 opa686 transimpedance amplifier. one transimpedance design ex- ample is shown on the front page of the data sheet. designs that require high bandwidth from a large area (high capaci- tance) detector with relatively low transimpedance gain will benefit from the low input voltage noise offered by the opa686. this input voltage noise will be peaked up over frequency at the output by the diode source capacitance, and can, in many cases, become the limiting factor to input sensitivity. the key elements of the design are the expected diode capacitance (c d ) with the reverse bias voltage (Cv b ) applied, the desired transimpedance gain, r f , and the gbp of the opa686 (1600mhz). figure 3 shows a design using a 50pf source capacitance diode and a 10k w transimpedance gain. with these three variables set (and including the parasitic input capacitance for the opa686 added to c d ), the feedback capacitor value (c f ) may be set to control the frequency response. where: i eq = equivalent input noise current if the output noise is bandlimited to f < 1/(2 p r f c d ) i n = input current noise for the op amp inverting input e n = input voltage noise for the op amp c d = diode capacitance f = bandlimiting frequency in hz (usually a post filter prior to further signal processing) evaluating this expression up to the feedback pole frequency at 15.5mhz for the circuit of figure 3, gives an equivalent input noise current of 6.4pa/ ? hz. this is much higher than the 1.8pa/ ? hz for just the op amp itself. this result is being dominated by the last term in the equivalent input noise expression. it is essential in this case to use a low voltage noise op amp. for example, if a slightly higher input noise voltage, but otherwise identical op amp were used instead of the opa686 in this application (say 2.0nv/ ? hz ), the total input-referred current noise would increase to 9.5pa/ ? hz. low gain compensation for improved sfdr where a low gain is desired, and inverting operation is acceptable, a new external compensation technique may be used to retain the full slew rate and noise benefits of the opa686 while giving increased loop gain and the associ- ated improvement in distortion offered by the decompen- sated architecture. this technique shapes the loop gain for good stability while giving an easily controlled second- order low pass frequency response. considering only the noise gain (non-inverting signal gain) for the circuit of figure 4, the low frequency noise gain, (ng 1 ) will be set by the resistor ratios while the high frequency noise gain (ng 2 ) will be set by the capacitor ratios. the capacitor values set both the transition frequencies and the high frequency noise gain. if this noise gain, determined by ng 2 = 1+c s /c f , is set to a value greater than the recommended minimum stable gain for the op amp and the noise gain pole, set by 1/r f c f , is placed correctly, a very well controlled, 2nd-order low pass frequency response will result. figure 3. wideband, low noise, transimpendance amplifier. to achieve a maximally flat 2nd-order butterworth fre- quency response, the feedback pole should be set to: 1/(2 p r f c f ) = ? (gbp/(4 p r f c d )) adding the common-mode and differential mode input ca- pacitance (1.0 + 2.0)pf to the 50pf diode source capacitance of figure 3, and targeting a 10k w transimpedance gain using the 1600mhz gbp for the opa686, will require a feedback pole set to 15.5mhz. this will require a total feedback capacitance of 1.0pf. typical surface-mount resistors have a parasitic capacitance of 0.2pf, leaving the required 0.8pf value shown in figure 3 to get the required feedback pole. this will give an approximate C3db bandwidth equal to: f C3db = ? (gbp/2 p r f c d )hz the example of figure 3 will give approximately 23mhz flat bandwidth using the 0.8pf feedback compensation. if the total output noise is bandlimited to a frequency less than the feedback pole frequency, a very simple expression for the equivalent input noise current can be derived as: figure 4. broadband low gain inverting external com- pensation. r f 500 w c s 27pf opa686 +5v ?v v o v i c f 2.9pf r g 250 w i eq = i n 2 + 4 kt r f + e n r f ? ? ? ? 2 + e n 2p c d f () 2 3 r f 10k w supply decoupling not shown c d 50pf l opa686 +5v ?v ? b i d v o = i d r f c f 0.8pf
10 opa686 12 9 6 3 0 ? ? ? ?2 ?5 ?8 frequency (mhz) gain (3db/div) 1 10 100 500 170mhz to choose the values for both c s and c f , two parameters and only three equations need to be solved. the first parameter is the target high frequency noise gain ng 2 , which should be greater than the minimum stable gain for the opa686. here, a target ng 2 of 10.5 will be used. the second parameter is the desired low frequency signal gain, which also sets the low frequency noise gain ng 1 . to simplify this discussion, we will target a maximally flat second-order low pass butterworth frequency response (q = 0.707). the signal gain of C2 shown in figure 4 will set the low frequency noise gain to ng 1 = 1 + r f /r g (= 3 in this example). then, using only these two gains and the gbp for the opa686 (1600mhz), the key frequency in the compensation can be determined as: physically, this z 0 (10.6mhz for the values shown above) is set by 1/(2 p ? r f (c f + c s )) and is the frequency at which the rising portion of the noise gain would intersect unity gain if projected back to 0db gain. the actual zero in the noise gain occurs at ng 1 ? z 0 and the pole in the noise gain occurs at ng 2 ? z 0 . since gbp is expressed in hz, multiply z 0 by 2 p and use this to get c f by solving: finally, since c s and c f set the high frequency noise gain, determine c s by [using ng 2 = 10.5]: the resulting closed-loop bandwidth will be approximately equal to: for the values shown in figure 4, the f C3db will be approxi- mately 130mhz. this is less than that predicted by simply dividing the gbp product by ng 1 . the compensation network controls the bandwidth to a lower value while providing the full slew rate at the output and an excep- tional distortion performance due to increased loop gain at frequencies below ng 1 ? z 0 . the capacitor values shown in figure 4 are calculated for ng 1 = 3 and ng 2 = 10.5 with no adjustment for parasitics. figure 5 shows the measured frequency response for the circuit of figure 4. this shows the expected gain of C2 (6db) with exceptional flatness through 70mhz and a C3db bandwidth of 170mhz. measured distortion into a 100 w load shows > 5db improvement through 20mhz over the performance shown in the typical performance curves. into a 500 w load, the 5mhz, 2vp-p, 2nd harmonic improves from C90dbc to C96dbc. z o = gbp ng 1 2 1 ng 1 ng 2 ? ? ? ? 12 ng 1 ng 2 ? ? figure 5. g = C2 frequency response with external compensation. low noise figure, high dynamic range if amplifier the low input noise voltage of the opa686 and its high two-tone intercept can be used to good advantage as a fixed gain if amplifier. while input noise figures in the 10db range (for a matched 50 w input) are easily achieved with just opa686 alone, figure 6 shows a technique which reduces the noise figure even further while providing a broadband, low gain if amplifier stage using the opa686. figure 6. low noise figure if amplifier. bringing the signal in through a step-up transformer to the inverting input gain resistor has several advantages for the opa686. first, grounding the non-inverting input elimi- nates the contribution of the non-inverting input current noise to the output noise. secondly, the non-inverting input voltage noise of the op amp is actually attenuated if reflected to the input side of r g . using the 1:2 (turns ratio) step up transformer reflects the 50 w source impedance at c f = 1 2p r f z o ng 2 c s = ng 2 1 () c f f 3 db @ z o gbp (= 2.86pf) (= 27.2pf) (= 130mhz) opa686 +5v ?v r g 200 w r f 1k w 50 w v o 2pf 20pf 50 w source 50 w load 1:2
11 opa686 the primary through to the secondary as a 200 w source impedance and likewise, the 200 w r g resistor is reflected through to the transformer primary as a 50 w input match- ing impedance. the noise gain (ng) to the amplifier output is then 1+ 1000/400 = 3.5v/v. taking the op amps 1.3nv/ ? hz input voltage noise times this noise gain to the output, then reflecting this noise term to the input side of the r g resistor, divides it by 5. this gives a net gain of 0.7 for the non-inverting input voltage noise when reflected to the input point for the op amp circuit. this is further reduced when referred back to the transformer primary. the 14db gain to the matched load for the circuit of figure 6 is precisely controlled ( 0.2db) and gives a 6db noise figure at the input of the transformer. the dc noise gain for this circuit (3.5) is below the specified minimum stable gain. this will improve the distortion performance at frequencies below 20mhz from those shown in the typical performance curves. adding the inverting compensation capacitors holds this configuration stable as described in the previous section. measured results show 140mhz small-signal bandwidth for the circuit of figure 6 with 0.1db flatness through 50mhz. the opa686 will easily deliver a 2vp-p adc full-scale input at the matched 50 w load. two-tone testing at 20mhz for the circuit of figure 6 (1vp-p for each test tone) shows that the two-tone intermodulation intercept has improved to 40dbm versus the 35dbm shown in the typical perfor- mance curves, giving a 72dbc sfdr for the two 4dbm test tones at the load . design-in tools demonstration boards two pc boards are available to assist in the initial evaluation of circuit performance using the opa686 in its two package styles. both of these are available free as an unpopulated pc board delivered with descriptive documentation. the sum- mary information for these boards is shown in the table below. board literature part request product package number number opa686u 8-pin so-8 dem-opa68xu mkt-351 opa686n 5-lead sot23-5 dem-opa6xxn mkt-348 contact the burr-brown applications support line to request any of these boards. macromodels and applications support computer simulation of circuit performance using spice is often useful when analyzing the performance of analog circuits and systems. this is particularly true for video and rf amplifier circuits where parasitic capacitance and induc- tance can have a major effect on circuit performance. a spice model for the opa686 is available through either the burr-brown internet web page (http://www.burr-brown.com) or as one model on a disk from the burr-brown applications department (1-800-548-6132). the applications department is also available for design assistance at this number. these models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. they do not do as well in predicting the har- monic distortion characteristics. these models do not at- tempt to distinguish between the package types in their small-signal ac performance. operating suggestions setting resistor values to minimize noise the opa686 provides a very low input noise voltage while requiring a low 12ma quiescent current. to take full advan- tage of this low input noise, careful attention to the other possible noise contributors is required. figure 7 shows the op amp noise analysis model with all the noise terms included. in this model, all the noise terms are taken to be noise voltage or current density terms in either nv/ ? hz or pa/ ? hz. the total output spot noise voltage can be computed as the square root of the squared contributing terms to the output noise voltage. this computation adds all the contributing noise powers at the output by superposition, then takes the square root to get back to a spot noise voltage. equation 1 shows the general form for this output noise voltage using the terms shown in figure 7. equation 1 dividing this expression by the noise gain (ng = 1+r f /r g ) will give the equivalent input-referred spot noise voltage at the non-inverting input as shown in equation 2. equation 2 4kt r g r g r f r s opa686 i bi e o i bn 4kt = 1.6e ?0j at 290? e rs e ni 4ktr s ? 4ktr f ? e o = e ni 2 + i bn r s () 2 +4 ktr s () ng 2 + i bi r f () 2 +4 ktr f ng e n = e ni 2 + i bn r s () 2 +4 ktr s + i bi r f ng ? ? ? 2 + 4 ktr f ng figure 7. op amp noise analysis model.
12 opa686 inserting high resistor values into eq. 2 can quickly domi- nate the total equivalent input referred noise. a 105 w source impedance on the non-inverting input will add a johnson voltage noise term equal to that of the amplifier itself. as a simplifying constraint, set r g = r s in eq. 2 and assume an r s /2 source impedance at the non-inverting input (where r s is the signals source impedance with another matching r s to ground on the non-inverting input). this results in eq. 3, where ng > 10 has been assumed to further simplify the expression. equation 3 evaluating this expression for r s = 50 w will give a total equivalent input noise of 1.7nv/ ? hz. note that the ng has dropped out of this expression. this is valid only for ng > 10 as will typically be required by stability considerations. frequency response control voltage feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. in theory, this relationship is described by the gain bandwidth product (gbp) shown in the specifications. ideally, dividing gbp by the non-inverting signal gain (also called the noise gain, or ng) will predict the closed-loop bandwidth. in practice, this only holds true when the phase margin approaches 90 , as it does in high gain configurations. at low gains (increased feedback factor), most high speed amplifiers will exhibit a more complex response with lower phase margin. the opa686 is compensated to give a maximally flat 2nd-order butterworth closed-loop response at a non-inverting gain of +10 (figure 1). this results in a typical gain of +10 band- width of 250mhz, far exceeding that predicted by dividing the 1600mhz gbp by 10. increasing the gain will cause the phase margin to approach 90 and the bandwidth to more closely approach the predicted value of (gbp/ng). at a gain of +40, the opa686 will show the 40mhz bandwidth predicted using the simple formula and the typical gbp of 1600mhz. inverting operation offers some interesting opportunities to increase the available gbp. when the source impedance is matched by the gain resistor (figure 2), the signal gain is (1+r f /r g ) while the noise gain for bandwidth purposes is (1 + r f /2r g ). this cuts the noise gain almost in half, increas- ing the minimum stable gain for inverting operation under these condition to C12 and the equivalent gbp to 3.2ghz. driving capacitive loads one of the most demanding and yet very common load conditions for an op amp is capacitive loading. often, the capacitive load is the input of an a/d converter, including additional external capacitance which may be recommended to improve a/d linearity. a high speed, high open-loop gain amplifier like the opa686 can be very susceptible to de- creased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. when the amplifiers open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. several external solutions to this problem have been suggested. when the primary considerations are frequency response flatness, pulse response fidelity and/or distortion, the sim- plest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. this does not eliminate the pole from the loop re- sponse, but rather shifts it and adds a zero at a higher frequency. the additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. the typical performance curves show the recommended r s vs capacitive load and the resulting frequency response at the load. parasitic capacitive loads greater than 2pf can begin to degrade the performance of the opa686. long pc board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. always consider this effect carefully, and add the recommended series resistor as close as possible to the opa686 output pin (see board layout guidelines). the criterion for setting this r s resistor is a maximum bandwidth, flat frequency response at the load. for the opa686 operating in a gain of +10, the frequency response at the output pin is very flat to begin with, allowing relatively small values of r s to be used for low capacitive loads. as the signal gain is increased, the unloaded phase margin will also increase. driving capacitive loads at higher gains will re- quire lower r s values than those shown for a gain of +10. distortion performance the opa686 is capable of delivering an exceptionally low distortion signal at high frequencies over a wide range of gains. the distortion plots in the typical performance curves show the typical distortion under a wide variety of condi- tions. most of these plots are limited to 110db dynamic range. the opa686s distortion, driving a 500 w, load does not rise above C90dbc until either the signal level exceeds 2.0vp-p and/or the fundamental frequency exceeds 5mhz. distortion in the audio band is < C120dbc. generally, until the fundamental signal reaches very high frequencies or powers, the 2nd harmonic will dominate the distortion with negligible a 3rd harmonic component. focus- ing then on the 2nd harmonic, increasing the load impedance improves distortion directly. remember that the total load includes the feedback network; in the non-inverting configu- ration, this is sum of r f + r g , while in the inverting configuration, it is just r f (figures 1 and 2). increasing output voltage swing increases harmonic distortion directly. a 6db increase in output swing will generally increase the 2nd harmonic 12db and the 3rd harmonic 18db. increasing the signal gain will also increase the 2nd harmonic distor- tion. again, a 6db increase in gain will increase the 2nd and 3rd harmonic by approximately 6db even with constant e n = e ni () 2 + 5 4 i b r s () 2 +4 kt 3 r s 2 ? ? ?
13 opa686 output power and frequency. finally, the distortion increases as the fundamental frequency increases due to the rolloff in the loop gain with frequency. conversely, the distortion will improve going to lower frequencies down to the dominant open-loop pole at approximately 100khz. starting from the C82dbc 2nd harmonic for a 5mhz, 2vp-p fundamental into a 200 w load at g = +10 (from the typical performance curves), the 2nd harmonic distortion for frequencies lower than 100khz will be approximately C82dbc C 20log(5mhz/ 100khz) = C116dbc. the opa686 has extremely low 3rd-order harmonic distor- tion. this also gives a high two-tone, 3rd-order intermodulation intercept as shown in the typical perfor- mance curves. this intercept curve is defined at the 50 w load when driven through a 50 w matching resistor to allow direct comparisons to rf mmic devices. this matching network attenuates the voltage swing from the output pin to the load by 6db. if the opa686 drives directly into the input of a high impedance device, such as an adc, the 6db attenuation is not taken. under these conditions, the inter- cept will increase by a minimum 6dbm. the intercept is used to predict the intermodulation spurious for two, closely- spaced frequencies. if the two test frequencies, f 1 and f 2 , are specified in terms of average and delta frequency, f o = (f 1 + f 2 )/2 and d f = |f 2 C f 1 |/2, the two 3rd-order, close-in spurious tones will appear at f o 3 ? d f. the difference between two equal test-tone power levels and these intermodulation spurious power levels is given by d dbc = 2 ? (im3 C p o ) where im3 is the intercept taken from the typical performance curve and p o is the power level in dbm at the 50 w load for one of the two closely-spaced test frequencies. for instance, at 5mhz the opa686 at a gain of +10 has an intercept of 48dbm at a matched 50 w load. if the full envelope of the two frequencies needs to be 2vp-p, this requires each tone to be 4dbm. the 3rd-order intermodulation spurious tones will then be 2 ? (48 C 4) = 88dbc below the test-tone power level (C84dbm). if this same 2vp-p, two- tone envelope were delivered directly into the input of an adcwithout the matching loss or the loading of the 50 w networkthe intercept would increase to at least 54dbm. with the same signal and gain conditions, but now driving directly into a light load, the spurious tones will then be at least 2 ? (54 C 4) = 100dbc below the 4dbm test-tone power levels centered on 5mhz. dc accuracy and offset control the opa686 can provide excellent dc signal accuracy due to its high open-loop gain, high common-mode rejection, high power supply rejection, and low input offset voltage and bias current offset errors. to take full advantage of its low 1.5mv input offset voltage, careful attention to input bias current cancellation is also required. the low noise input stage of the opa686 has a relatively high input bias current (10 m a typical into the pins) but with a very close match between the two input currentstypically 100na input offset current. the total output offset voltage may be reduced considerably by matching the source impedances looking out of the two inputs. for example, one way to add bias current cancellation to the circuit of figure 1 would be to insert a 20 w series resistor into the non-inverting input from the 50 w terminating resistor. when the 50 w source resistor is dc-coupled, this will increase the source resis- tances for the non-inverting input bias current to 45 w . since this is now equal to the resistance looking out of the inverting input (r f || r g ), the circuit will cancel the gains for the bias currents to the output leaving only the offset current times the feedback resistor as a residual dc error term at the output. using the 453 w feedback resistor, this output error will now be less than 0.9 m a ? 453 w = 0.4mv over the full temperature range. a fine-scale, output offset null, or dc operating point adjustment, is often required. numerous techniques are available for introducing a dc offset control into an op amp circuit. most of these techniques eventually reduce to setting up a dc current through the feedback resistor. one key consideration to selecting a technique is to insure that it has a minimal impact on the desired signal path frequency response. if the signal path is intended to be non-inverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. if the signal path is intended to be inverting, applying the offset control to the non-inverting input can be considered. for a dc-coupled inverting input signal, this dc offset signal will set up a dc current back into the source that must be considered. an offset adjustment placed on the inverting op amp input can also change the noise gain and frequency response flatness. figure 8 shows one example of an offset adjustment for a dc-coupled signal path that will have minimum impact on the signal frequency response. in this case, the input is brought into an inverting gain resistor with the dc adjustment an additional current summed into the inverting node. the resistor values setting this offset adjust- ment are much larger than the signal path resistors. this will insure that this adjustment has minimal impact on the loop gain and hence, the frequency response. figure 8. dc-coupled, inverting gain of C20, with output offset adjustment. r f 1k w ?00mv output adjustment = ? = ?0 supply decoupling not shown 5k w 5k w 48 w 0.1? r g 50 w v i 20k w 10k w 0.1? ?v +5v opa686 +5v ?v v o v o v i r f r g
14 opa686 thermal analysis the opa686 will not require heatsinking or airflow in most applications. maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. in no case should the maximum junction temperature be allowed to exceed +175 c. operating junction temperature (t j ) is given by t a + p d ? q ja . the total internal power dissipation (p d ) is the sum of quiescent power (p dq ) and additional power dissipated in the output stage (p dl ) to deliver load power. quiescent power is simply the specified no-load supply current times the total supply voltage across the part. p dl will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). under this worst-case condition, p dl = v s 2 /(4 ? r l ) where r l includes feedback network loading. note that it is the power in the output stage and not in the load that determines internal power dissipation. as a worst-case example, compute the maximum t j using an opa686n (sot23-5 package) in the circuit of figure 1 operating at the maximum specified ambient temperature of +85 c and driving a grounded 100 w load at +2.5v dc . p d = 10v (13.9ma) + 5 2 /(4 ? (100 w || 500 w )) = 214mw maximum t j = +85 c + (0.21w ? 150 c/w) = 117 c board layout achieving optimum performance with a high frequency amplifier like the opa686 requires careful attention to board layout parasitics and external component types. rec- ommendations that will optimize performance include: a) minimize parasitic capacitance to any ac ground for all of the signal i/o pins. parasitic capacitance on the output and inverting input pins can cause instability: on the non-inverting input, it can react with the source impedance to cause unintentional bandlimiting. to reduce unwanted capacitance, a window around the signal i/o pins should be opened in all of the ground and power planes around those pins. otherwise, ground and power planes should be unbro- ken elsewhere on the board. b) minimize the distance (< 0.25") from the power supply pins to high frequency 0.1 m f decoupling capaci- tors. at the device pins, the ground and power plane layout should not be in close proximity to the signal i/o pins. avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. the power supply connections should always be decoupled with these capacitors. larger (2.2 m f to 6.8 m f) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. these may be placed somewhat farther from the device and may be shared among several devices in the same area of the pc board. c) careful selection and placement of external compo- nents will preserve the high frequency performance of the opa686. resistors should be a very low reactance type. surface-mount resistors work best and allow a tighter over- all layout. metal-film and carbon composition, axially-leaded resistors can also provide good high frequency performance. again, keep their leads and pc board trace length as short as possible. never use wirewound type resistors in a high frequency application. since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. other network components, such as non-inverting input termination resis- tors, should also be placed close to the package. where double-side component mounting is allowed, place the feed- back resistor directly under the package on the other side of the board between the output and inverting input pins. even with a low parasitic capacitance shunting the external resis- tors, excessively high resistor values can create significant time constants that can degrade performance. good axial metal-film or surface-mount resistors have approximately 0.2pf in shunt with the resistor. for resistor values > 1.5k w , this parasitic capacitance can add a pole and/or a zero below 500mhz that can effect circuit operation. keep resistor values as low as possible consistent with load driving con- siderations. it has been suggested here that a good starting point for design would be set the r g be set to 50 w . doing this will automatically keep the resistor noise terms low, and minimize the effect of their parasitic capacitance. d) connections to other wideband devices on the board may be made with short direct traces or through on- board transmission lines. for short connections, consider the trace and the input to the next device as a lumped capacitive load. relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. estimate the total capacitive load and set r s from the plot of recommended r s vs capacitive load. low parasitic capacitive loads (< 5pf) may not need an r s since the opa686 is nominally compensated to operate with a 2pf parasitic load. higher parasitic capacitive loads without an r s are allowed as the signal gain increases (increasing the unloaded phase margin). if a long trace is required, and the 6db signal loss intrinsic to a doubly- terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ecl design handbook for microstrip and stripline layout techniques). a 50 w environ- ment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. with a character- istic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the opa686 is used as well as a terminating shunt resistor at the input of the destination device. remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effec- tive impedance should be set to match the trace impedance. if the 6db attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot
15 opa686 of r s vs capacitive load. this will not preserve signal integrity as well as a doubly-terminated line. if the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) socketing a high speed part like the opa686 is not recommended. the additional lead length and pin-to-pin capacitance introduced by the socket can create an ex- tremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. best results are obtained by soldering the opa686 onto the board. input and esd protection the opa686 is built using a very high speed complemen- tary bipolar process. the internal junction breakdown volt- ages are relatively low for these very small geometry de- vices. these breakdowns are reflected in the absolute maxi- mum ratings table. all device pins are protected with internal esd protection diodes to the power supplies as shown in figure 9. external pin +v cc ? cc internal circuitry figure 9. internal esd protection. these diodes provide moderate protection to input overdrive voltages above the supplies as well. the protection diodes can typically support 30ma continuous current. where higher currents are possible (e.g., in systems with 15v supply parts driving into the opa686), current-limiting series resis- tors should be added into the two inputs. keep these resistor values as low as possible since high values degrade both noise performance and frequency response.
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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